1. Field of the Invention
The present invention relates to a method of forming a thin film transistor (TFT), and more particularly, to a method of forming a low temperature polysilicon thin film transistor (LTPS TFT) having improved electrical characteristics and uniformity by utilizing a laser crystallization (LC) process.
2. Description of the Prior Art
Currently, a liquid crystal display (LCD) is the most popular flat panel display technique. The applications for liquid crystal displays are extensive, such as mobile phones, digital cameras, video cameras, notebooks, and monitors. Due to high quality display requirements and the expansion of new application fields, the LCD has developed toward high quality, high resolution, high brightness, and low price. Development of low temperature polysilicon thin film transistors (LTPS TFTs), to be used in active matrix LCD, is a break-through in achieving the above objectives.
Please refer to FIG. 1 to FIG. 4 that are schematic diagrams of fabricating an LTPS-TFT 26 according to the prior art. The prior art LTPS-TFT 26 is fabricated on an insulation substrate 10. The insulation substrate 10, composed of transparent materials, may be a glass substrate or a quartz substrate.
Referring to FIG. 1, an amorphous silicon thin film (a-Si thin film, not shown) is formed on the insulation substrate 10 first. Then an excimer laser annealing (ELA) process is performed to crystallize the amorphous silicon thin film (not shown) into a polysilicon layer 12. The polysilicon layer 12 comprises a source region 13, a drain region 14, and a channel region 15. The polysilicon layer 12, also called an active layer, is used as a channel when the LTPS-TFT 26 is turned on.
Since the quality of the amorphous silicon thin film (not shown) is a determinative factor for the characteristics of the subsequent formed polysilicon layer 12, all of the parameters during the amorphous silicon thin film deposition process need to be strictly controlled. The amorphous silicon thin film with low hydrogen content, high thickness uniformity, and low surface roughness is thus formed. Moreover, the amorphous silicon thin film is melted and crystallized rapidly through absorption of the deep ultra-violet light during the excimer laser annealing process to form the polysilicon layer 12. Such a quick absorption due to the short laser pulse only affects the amorphous silicon thin film and will not affect the insulation substrate 10. Hence, the insulation substrate 10 is kept at a low temperature state.
As shown in FIG. 2, a plasma enhanced chemical vapor deposition (PECVD) process is thereafter performed to form a gate insulating layer (SiOxlayer) 16 having a thickness of 500˜1200 angstrom (Å) on the polysilicon layer 12. The gate insulating layer 16 may be single-layered structure, or a composite-layered structure, depending on design requirements. The material composition of the gate insulating layer 16 comprises silane-based silicon oxide (SiH4 based SiOx), tetra-ethyl-ortho-silicate based silicon oxide (TEOS-based SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). After that, a first sputtering process is performed to form a metal layer 18 on the gate insulating layer 16. The metal layer 18 may be a tungsten (W) layer, a chrome (Cr) layer, or another conductive metal layer.
As shown in FIG. 3, then a photoresist layer (not shown) is formed on the insulation substrate 10. A photolithography process is thereafter performed to define a gate pattern 22 in the photoresist layer (not shown). The gate pattern 22 is on the channel region 15. After that, a dry etching process is performed to remove portions of the metal layer 18 so as to form a gate 24 of the LTPS-TFT 26 on the gate insulating layer 16.
After removing the gate pattern 22, an ion implantation process is then performed to form a source 28 and a drain 32 of the LTPS-TFT 26, in the source region 13, and in the drain region 14 in the polysilicon layer 12 respectively by utilizing the gate 24 as a mask, as shown in FIG. 4. In the application of the thin film transistor (TFT), the series resistance of the source/drain must be low. An activation process is thus necessarily performed after the ion implantation process to highly activate the dopants in the source 28 and the drain 32. The activation process not only moves the ions to the correct lattice sites but also repairs the lattice defects incurred from the ion implantation process to complete the fabrication of the LTPS-TFT 26.
After completing the LTPS-TFT 26, a dielectric layer 34 is deposited. The dielectric layer 34 may be a single-layered dielectric layer or a composite-layered dielectric layer. Finally a photo-etching-process (PEP) is performed to form a contact hole 36 through the dielectric layer 34 and the gate insulating layer 16, on the source region 13 and the drain region 14 respectively, extending to the source 28 and the drain 32. The contact hole 36 is thereafter filled with conductive materials (not shown) to electrically connect the source 28 and the drain 32 to electrodes of the capacitor and the signal line respectively, according to the circuit design.
However, the prior art method of forming the LTPS-TFT 26 faces a very severe problem of difficulty in controlling the quality of the active polysilicon thin film on the channel region. In addition, many variables during the amorphous silicon thin film formation process and the crystallization process, such as the quality of the as-formed amorphous silicon thin film, the magnitude of the laser energy density, the spatial uniformity of the laser energy, the overlapping ratio of the laser pulse, the substrate temperature during the laser annealing process, and the atmosphere during the laser annealing process, will directly affect the grain size and the grain distribution after the crystallization process is completed. When process is not properly controlled, many small polysilicon thin film grains are generated in the active channel region after crystallization to result in considerable grain boundary.
Please refer to FIG. 5, which is a schematic diagram illustrating small polysilicon thin film grains 38 generated in the channel region 15 of the LTPS-TFT 26 shown in FIG. 3. As shown in FIG. 5, an unsatisfactory laser annealing process generates many polysilicon thin film grains 38 and considerable grain boundary 42 in the channel region 15. When the LTPS-TFT 26 is turned on, the considerable grain boundary 42 will trap electrons flowing through the channel region 15 to reduce the conductive current. When the LTPS-TFT 26 is turned off, electrons will be released to increase the leakage current. By continuous experiments and fine tuning, the crystallization situation of a single LTPS-TFT 26 may satisfy the expected criterion because a qualifying process condition discovered. However, a common laser crystallization process is not able to control the growing sites and the growing orientations of the polysilicon thin film grains 38 on an entire panel, which usually has several hundred thousand pixels or even several millions pixels.
In other words, the grains in the amorphous silicon thin film are randomly distributed resulting in inconsistency of electrical characteristics among the LTPS-TFTS, especially when the size of the low temperature polysillicon thin film transistor is continuously shrunk. Therefore, the process window of the laser crystallization process is usually very narrow. In addition, the laser crystallization process is a low temperature solid crystallization process. Since the solid crystallization usually takes a long time, the grains can only grow to a specific size. The amount of grain boundary is thus difficult to control, bringing limitation to the laser crystallization process.
Therefore, it is very important to develop a new structure to better control the growth sites and the growth orientations of the grains when applying the same laser crystallization process to crystallize the amorphous silicon thin film, to effectively improve the electrical characteristics and the uniformity of the LTPS-TFTS, and to enlarge the process window of the laser crystallization process.